Silicon carbide substrate and semiconductor device

ABSTRACT

To provide a silicon carbide substrate having at least one or more main surfaces, including: a plurality of encapsulated regions inside, wherein the plurality of encapsulated regions are distributed in a direction approximately parallel to one of the main surfaces, with each encapsulated region positioned at a distance of 100 nm or more and 100 μm or less from the main surfaces to inside a substrate, and each encapsulated region having a width of 100 nm or more and 100 μm or less in a direction parallel to the main surfaces.

TECHNICAL FIELD

The present invention relates to a silicon carbide substrate used for a high performance semiconductor device. Particularly, there is provided a silicon carbide substrate which has an extremely low planar defects density on a specific crystal surface, and which can be preferably utilized as a material of a power semiconductor device having high efficiency and high breakdown voltage.

DESCRIPTION OF RELATED ART

Silicon carbide has been used as a compound semiconductor material for high performance semiconductor device. However, in some cases, silicon carbide substrate includes high density of crystal defects.

A performance of the semiconductor device is significantly affected by such crystal defects included in the silicon carbide substrate. For example, the representative planar defects, such as an anti-phase boundary and a stacking fault, cause a current leak or dielectric breakdown and remarkably reduce the performance of a power semiconductor device. Therefore, reduction of such planar defects is the main issue for silicon carbide substrate applicable to the device use.

Some conventional methods for reducing the planar defects in silicon carbide substrate will be described hereafter. As a method for reducing the planar defect density during hetero-epitaxial growth of the silicon carbide on a Si substrate, one method for controlling a thickness of the silicon carbide shown in patent document 1, and the other method for using the Si substrate whose surface normal axis is slightly tilted from [001] direction, which is so-called misoriented-Si (001) substrate, shown in non-patent document 1, are given.

By using the misoriented-Si(001) substrate shown in non-patent document 1, the anti-phase boundaries disappear by controlling an orientation of a polar face. Moreover, according to this method, atomic-level steps are introduced at equal intervals in one direction, and therefore propagation of the planar defects in a direction vertical to the introduced steps (in a direction crossing the steps) can be prevented by the step-flow during the silicon carbide hetero-epitaxial growth.

However, it is insufficient to reduce the stacking faults density only by using this misoriented-Si substrate. Essentially, on silicon carbide (001) surface, stacking faults are propagated parallel to four equivalent {111} planes. When two counter-propagated stacking faults are merged during the silicon carbide epitaxial growth, only one of them can be propagated and the other is disappeared. This is so-called an annihilation mechanism between the counter-propagated stacking faults. By repeating this phenomenon, the stacking faults density can be reduced with increasing the silicon carbide growth thickness. However, in a case of the silicon carbide epitaxial growth on the misoriented-Si (001) substrate, the propagation of the stacking faults parallel to (111) plane is preferentially blocked by the steps, and the propagation of the stacking faults parallel to (−1-11) plane becomes dominant. As a result, the effect of annihilation is lost and complete elimination of the stacking faults is not achieved.

In order to effectively reduce both of the planar defects, the anti-phase boundary and the stacking fault with keeping the effect of annihilation, a technique of growing the silicon carbide on the Si (001) substrate on which the undulations are formed parallel with one direction, as shown in patent document 2 and non-patent document 2, is developed. A defects reducing mechanism with using this technique will be described hereafter.

When silicon carbide is grown on the Si substrate on which the undulations are formed parallel with [−110] direction shown in FIG. 9, which is named as the undulant-Si(001) substrate hereafter, the anti-phase boundaries disappear due to the same manner described in the silicon carbide epitaxial growth on the misoriented-Si(001) substrate.

Furthermore, when the silicon carbide is grown on the undulant-Si(001) substrate, the stacking faults density also can be reduced. Essentially, the stacking faults existed on the cubic silicon carbide (001) face are classified into two types by the difference of the polar face exposed on (001) surface. One is a stacking fault exposing a C-polar face on (001) surface and the other is exposing a Si-polar face.

Regarding the stacking fault exposing the C-polar face, its surface energy is relatively lower than that of (001) surface. Therefore, the stacking fault exposing C-polar face is instable on (001) surface and tends to be self-vanished during the silicon carbide epitaxial growth.

Regarding the stacking fault exposing the Si-polar face, on the other hand, its surface energy is relatively higher than that of (001) plane. Therefore, the stacking fault exposing the Si-polar face is relatively stable and tends to be remain on (001) surface. Such stable stacking fault exposing Si-polar face can be reduced by the following manner. FIG. 10 shows an enlarged (−110) cross-sectional image of the undulation formed on a Si(001) substrate. On the facing slopes formed on the undulant substrate 101, the stacking faults 103 keep a mirror symmetrical relation each other. Consequently, stacking faults are continuously annihilated without allowing anisotropy of the propagating direction of the stacking faults described in silicon carbide epitaxial growth on the misoriented-Si(001) substrate.

By using this technique, further reduction of stacking faults than using conventional misoriented-Si(001) substrate should be achieved concerning aforementioned two kinds of stacking faults.

However, when the silicon carbide is hetero-epitaxially grown on the undulant-Si(001) substrate, the stacking faults exposing the Si-polar face are still remained in spite of working the above-mentioned annihilation mechanism. This is because the stacking faults exposing the Si-polar face are continuously occurred due to a lattice strain generated during the crystal growth. During the silicon carbide epitaxial growth, two kinds of the lattice strain are mainly generated. One is caused by a temperature distribution in a substrate, and the other is caused by a lattice miss-matching due to annihilation of the stacking faults. If such strains become larger than the elastic limit strains of the silicon carbide, silicon carbide is plastically deformed to release the strains. This is the occurring mechanism of the strain-induced stacking faults. Namely, new stacking faults are occurred by the existence of such strains, while the stacking faults density is reduced by annihilation process.

In order to reduce the stacking faults exposing the Si-polar face, SBE (Switch-Back-Epitaxy) technique as shown in non-patent document 3 is developed. The SBE technique will be described hereafter.

FIG. 11 shows a lattice model of the staking fault exposing Si-polar face on a surface. As shown in FIG. 11, the stacking fault 112 included in the silicon carbide crystal 111 exposes Si-polar face 113 on a front surface, and C-polar face 114 on a back surface of the substrate. This fact indicates that an exposed surface of the stacking faults can be converted from Si-polar face to C-polar face by turning the substrate upside down. Since the C-polar face is instable and tends to be self-vanished during the crystal growth, the residual stacking faults exposing Si-polar face can be completely eliminated in principle by homoepitaxial growth of the cubic silicon carbide on the back surface of the substrate.

The stacking faults density is actually reduced by using SBE technique, however, complete elimination of the stacking faults is not achieved. This is because the additional stacking faults occurrence during a SBE growth process, which is mainly caused by the strains existing in the cubic silicon carbide substrate and a homo-epitaxial layer. Similarly to the silicon carbide epitaxial growth on the undulant-Si(001) substrate, two kinds of the strains, caused by the temperature distribution in the substrate surface and the lattice miss-matching due to annihilation of the stacking faults, are also generated during SBE growth. Hence, new stacking faults are continuously occurred in the silicon carbide layer to release such strains. Namely, it is quite difficult to fabricate the cubic silicon carbide substrate having extremely low stacking faults density, which is suitable for manufacture of the high performance device, without controlling the lattice strain generated during the crystal growth.

In a technique shown in patent document 3, the undulations are formed not only in one direction but also in a direction orthogonal thereto on Si (001) substrate. By using this technique, a smooth surface is obtained because the surface roughing due to the step-bunching oriented in one direction is avoidable by step-flow growth on the two directional steps formed at the slope of two orthogonal undulations. However, the off-angle is also introduced not only in one direction but also in a direction orthogonal thereto, control of the orientation of the polar-face shown in the aforementioned non-patent document 2 is deteriorated and hence elimination of the anti-phase boundaries is not achieved.

In patent document 4, the defect reducing technique for GaN epilayer is described. Firstly, the trigonal pyramid-like GaN domains are formed by GaN epitaxial growth through the equilateral triangular windows formed on SiO2 masked GaN seed layer on a sapphire substrate. The sides of these triangular windows correspond to three equivalent (11-20) planes. Subsequently, lateral crystal growth is performed on the trigonal pyramid-like GaN domains. Herein, many dislocations are vertically extended from a GaN seed layer to the pyramid-like domains.

By subsequent lateral growth, the dislocations which reach the slope of the pyramid-like GaN domains can be eliminate due to changing their extending direction from vertical to lateral direction. Consequently, reduction of dislocation density in the additional GaN epilayer is achieved. However, when the adjoining pyramid-like GaN domains are merged each other, the dislocations extending to lateral direction are changed their extending direction to vertical again. Consequently, high dislocation density region are formed on the surface of the additional GaN epilayer. Furthermore, the planar defect, such as stacking fault and anti-phase boundaries, propagate in parallel to a specific orientation and their propagation directions are independent of growth direction. Therefore, the propagation direction of the planar defects cannot be controlled through the growth direction.

As described above, even if the technique described in patent document 4 is applied to silicon carbide homoepitaxial growth, it is impossible to obtain the defect-free surface unless the anti-phase boundaries and the stacking faults in the substrate are completely eliminated before homoepitaxial growth.

PRIOR ART DOCUMENT Patent Document Patent Document 1:

-   Examined Patent Publication No. 1994-41400

Patent Document 2:

-   Japanese Patent Laid Open Publication No. 2000-178740

Patent Document 3:

-   Japanese Patent Laid Open Publication No. 2002-201099

Patent Document 4:

-   Japanese Patent Laid Open Publication No. 2001-257166

Non-Patent Document Non-Patent Document 1:

-   K. Shibahara, S. Nishino, H. Matsunami, Appl. Phys. Lett. 50 (1987)     PP. 1888-1890

Non-Patent Document 2:

-   H. Nagasawa, T. Kawahara, K. Yagim, Mater. Sci. Forum 389-393 (2002)     pp. 319-322

Non-Patent Document 3:

-   K. Yagi, T. Kawahara, N. Hatta and H. Nagasawa: Mater. Sci. Forum     527-529 (2006) p. 291

SUMMARY OF THE INVENTION Problem to be Solved by the Invention

In view of the above-described problem, the present invention is provided. The object of the present invention is to provide a silicon carbide substrate with low planar defects density for a high performance semiconductor device use. This object is achieved by reducing planar defects density without allowing anisotropy of propagating direction of the stacking faults, and blocking propagation of the stacking faults caused by a lattice strain and a thermal strain during crystal growth.

Means for Solving the Problem

In order to solve the above-described problem, the present invention proposes the following matters.

(1) The present invention provides a silicon carbide substrate (corresponding to a silicon carbide substrate 1 of FIG. 1) having at least one or more main surfaces (corresponding to main surfaces 12 of FIG. 1 for example), comprising:

a plurality of encapsulated regions inside (corresponding to encapsulated regions 13 of FIG. 1 for example),

-   -   wherein the plurality of encapsulated regions are distributed in         a direction approximately parallel to one of the main surfaces,         with each encapsulated region positioned at a distance of 100 nm         or more and 100 μm or less from the main surfaces to inside a         substrate, and each encapsulated region having a width of 100 nm         or more and 100 μm or less in a direction parallel to the main         surfaces.         (2) The present invention provides the silicon carbide substrate         according to the silicon carbide substrate of (1), wherein each         encapsulated region is formed including at least one of silicon,         carbon, nitrogen, hydrogen, helium, neon, argon, krypton, and         xenon.         (3) The present invention provides the silicon carbide substrate         according to the silicon carbide substrate of (1), wherein the         encapsulated region is hollow.         (4) The present invention provides the silicon carbide substrate         according to the silicon carbide substrate of any one of (1) to         (3), wherein silicon carbide that forms the silicon carbide         substrate is a plate-shaped single crystal.         (5) The present invention provides the silicon carbide substrate         according to the silicon carbide substrate of any one of (1) to         (4), wherein silicon carbide that forms the silicon carbide         substrate (corresponding to a cubic silicon carbide 11 of FIG. 1         for example) is a cubic silicon carbide, with the main surface         formed as (001) plane, and side walls of the encapsulated         regions formed in parallel to {110} plane.         (6) The present invention provides the silicon carbide substrate         according to the silicon carbide substrate of any one of (1) to         (4), wherein silicon carbide that forms the silicon carbide         substrate (corresponding to a cubic silicon carbide 11 of         FIG. 1) is a cubic silicon carbide, with the main surface formed         as (111) plane, and side walls of the encapsulated regions         formed in parallel to {111} plane.         (7) The present invention provides the silicon carbide substrate         according to the silicon carbide substrate of any one of (1) to         (4), wherein silicon carbide that forms the silicon carbide         substrate (corresponding to a cubic silicon carbide 11 of         FIG. 1) is a cubic silicon carbide, with the main surface formed         as (111) plane, and side walls of the encapsulated regions         formed in parallel to {110} plane or {211} plane.         (8) The present invention provides the silicon carbide substrate         according to the silicon carbide substrate of any one of (1) to         (4), wherein silicon carbide that forms the silicon carbide         substrate is a hexagonal silicon carbide, with the main surface         formed as {0001} plane, and side walls of the encapsulated         regions formed in parallel to {11-20} plane or {−1100} plane.         (9) The present invention provides the silicon carbide substrate         according to the silicon carbide substrate of any one of (1) to         (8), wherein a width of the encapsulated region in a direction         vertical to the main surfaces is five times or more of its width         in a direction parallel to at least one of the main surfaces,         and a cross-sectional area of the encapsulated region viewed         from a direction parallel to the main surface is 1/10 or less of         the area of the main surfaces.         (10) The present invention provides a semiconductor device using         the silicon carbide substrate according to the silicon carbide         substrate of any one of (1) to (9), wherein a silicon carbide         layer having the same structure as a structure of the silicon         carbide (corresponding to the cubic silicon carbide 11 of         FIG. 1) that forms the silicon carbide substrate, is formed on         the main surface, and an internal electric field is formed on         the silicon carbide layer.         (11) The present invention provides a method for manufacturing a         silicon carbide substrate, comprising the steps of

forming a plurality of isolated regions having {110} plane as side walls on a silicon carbide substrate with (001) plane as a front surface; and

performing homo-epitaxial growth on the silicon carbide substrate,

wherein the step of performing homo-epitaxial growth includes the step of satisfying formula (2) described below:

r _(g[001])/tan 54.7°−r _(g[110])>0  (2)

wherein r_(g[001]) represents a growth rate in [001] direction, and r_(g[110]) represents a growth rate in [110] direction.

Advantage of the Invention

Conventionally, to reduce stacking faults density, the annihilation process between the counter-propagated stacking faults has been utilized. However, the probability of occurrence of the annihilation is proportional to the residual stacking faults density, and therefore as the number of residual stacking faults is reduced, a defect reduction effect (decreasing rate of stacking faults density per unit thickness) is also reduced, and is finally lost.

On the other hand, according to the present invention, encapsulated regions are introduced in a silicon carbide substrate to reduce the stacking faults density without depending on the above-mentioned annihilation process. By forming the encapsulated regions in which made of a vacuum space, hydrogen, inert gas, or a different material from a single crystal silicon carbide, the encapsulated regions can act as obstacles and inhibit the propagation of the stacking faults. In principle, the stacking faults can be propagated to a specific direction only in a single crystal. When the stacking faults propagating in a single crystal silicon carbide reach the encapsulated regions, their propagation is completely blocked at the interface between a single crystal silicon carbide and the encapsulated regions. Consequently, a defect-free surface is obtained without annihilation process, in other words, without generation of the lattice strain caused by the annihilation of the stacking faults.

Furthermore, since the Young modulus of the encapsulated regions is less than that of the silicon carbide, a thermal strain or a lattice strain generated during the crystal growth can be absorbed by the encapsulated regions. Even if the stacking faults are generated, their propagation is prevented at the interface as above described. Thus, by using the present invention, effective reduction of the stacking faults is achieved without affection of some lattice strains generated during the crystal growth.

Preferably, each encapsulated region is constituted including at least one of the silicon, carbon, nitrogen, hydrogen, helium, neon, argon, krypton, and xenon. Wherein, the hollow region also includes a vacuum state.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a silicon carbide substrate according to the present invention.

FIG. 2 is a plane-view of a front surface of a cubic silicon carbide substrate covered with the lattice-shaped SiO₂ mask according to a second embodiment of the present invention.

FIG. 3 is a cross-sectional view of the cubic silicon carbide substrate.

FIG. 4 is a cross-sectional view of the cubic silicon carbide substrate.

FIG. 5 is a cross-sectional view of the cubic silicon carbide substrate.

FIG. 6 is a cross-sectional view of a cubic silicon carbide substrate according to a third embodiment of the present invention.

FIG. 7 is a cross-sectional view of the cubic silicon carbide substrate.

FIG. 8 is a cross-sectional view of the cubic silicon carbide substrate.

FIG. 9 is an overview of a Si substrate with undulations having ridges formed in parallel to [−110] direction, according to a conventional example.

FIG. 10 is a cross-sectional view of the stacking faults distribution in the silicon carbide epilayer grown on the Si substrate with undulations.

FIG. 11 is a lattice image of the stacking fault in the cubic silicon carbide.

FIG. 12 is a schematic image for describing the mechanism of reducing the stacking faults density.

FIG. 13 is a schematic image for describing the mechanism of reducing the stacking faults density.

MODES FOR CARRYING OUT THE INVENTION

Embodiments of the present invention will be described hereafter with some related drawings. Note that the components exemplified in the aforementioned each embodiment can be completely or partially replaced with the existing ones. Accordingly, the components of the present invention is not limited within a scope of the claims by the description of the aforementioned each embodiment.

FIG. 1 is a cross-sectional view of a silicon carbide substrate according to the present invention. A main surface 12, being a largest portion of the exposed surfaces of the silicon carbide substrate 1, is formed in parallel to (001) face. In addition, the silicon carbide substrate 1 is a plate-shaped crystal with a back surface in parallel to the main surface 12.

Encapsulated regions 13 are distributed in an approximately parallel with the main surface 12 and preferably the plurality of encapsulated regions 13 exist uniformly inside of a cubic silicon carbide 11, which is a component of the silicon carbide substrate 1. Furthermore, a plurality of encapsulated regions 13 are distributed uniformly within 100 μm, preferably within 50 μm, and further preferably within 20 μm below the main surface 12. Preferably, each encapsulated region 13 is constituted including at least one of silicon, carbon, nitrogen, hydrogen, helium, neon, argon, krypton, and xenon, or is formed as a hollow region (such as vacuum space). Furthermore, a layer in which the encapsulated regions 13 are distributed is approximately parallel to the main surface 12. The side walls of the encapsulated regions 13, those who are defined as the surfaces not approximately parallel to the main surface 12, are approximately parallel to {110} planes.

Wherein, in order to effectively reduce the stacking faults density, it is necessary to satisfy the following geometrical condition that all stacking faults 14 are merged with the encapsulated regions 13. Specifically, as shown in FIG. 1, when an interval between the adjacent encapsulated regions is represented by W, a height of the encapsulated region 13 is represented by H, and an interior angle between the stacking fault 14 and the side wall of the encapsulated region 13 is represented by 9, the following formula (1) should be satisfied.

$\begin{matrix} \left\lbrack {{Formula}\mspace{14mu} 1} \right\rbrack & \; \\ {H \geq \frac{W}{\tan \; \theta}} & {{Formula}\mspace{14mu} (1)} \end{matrix}$

According to the above-described formula (1), the stacking faults density can be effectively reduced if a closest-packed plane to which the stacking faults 14 are propagated and the sidewall of encapsulated regions 13 are not parallel to each other, and the interior angle θ between the stacking faults 14 and the encapsulated regions 13 is larger than 0 degree and less than 90 degrees.

As described above, in the silicon carbide substrate 1, the main surface 12 is parallel to (001) face, and the side walls of the encapsulated region 13 are approximately parallel to {110} planes. On the other hand, the stacking faults 14 included in the cubic silicon carbide 11 are propagated in parallel to {111} planes corresponding to the closest-packed plane. Therefore, the interior angle θ between the stacking faults 14 and the encapsulated regions 13 will be 35.3 degrees.

Wherein, each of the dimensions concerning the encapsulated region 13, such as its interval W, its height H, and its width in the parallel direction to the main surface, represented by S, is desirable to be satisfy the following conditions, respectively. As for the interval W, it is desirable to be 100 nm or more and 100 μm or less, preferably 1 μm or more and 50 μm or less, and further preferably 2 μm or more and 20 μm or less in length. This is because when interval W is extremely small, processing of formation of the encapsulated regions 13 becomes to be difficult. Furthermore, a substrate resistance increases due to increasing of the volume occupancy of the encapsulated regions 13 in the substrate. When interval W is extremely large, the height H is also required to be extremely large value to satisfy the formula (1). Consequently, the thermal strain can't be completely absorbed due to decreasing of the volume occupancy of the encapsulated regions 13 in the substrate.

As for the height H, its value is given by the interval W and formula (1). When the height H is extremely small, processing of formation of the encapsulated regions 13 becomes difficult because the extremely small value of the interval W is required to satisfy the formula (1). Furthermore, the thermal strain can't be completely absorbed due to decreasing of the volume occupancy of the encapsulated regions 13 in the substrate. When the height H is extremely large (for example, when height H is 100 μm or more), processing of formation of the encapsulated regions 13 becomes difficult. Furthermore, a substrate resistance increases due to increasing of the volume occupancy of the encapsulated regions 13 in the substrate.

As for the width S, when the width S is extremely small, processing of formation of the encapsulated regions 13 becomes difficult. Furthermore, the thermal strain can't be completely absorbed due to decreasing of the volume occupancy of the encapsulated regions 13 in the substrate. When the width S is extremely large, a substrate resistance increases due to increasing of the volume occupancy of the encapsulated regions 13 in the substrate. Furthermore, it becomes difficult to form the encapsulated regions 13 with satisfying the desired values of the interval W. Therefore, the width S is also desirable to be 100 nm or more and 100 μm or less, preferably 1 μm or more and 50 μm or less, and further preferably 2 μm or more and 20 μm or less in length.

In addition to the above described dimensions of the encapsulated regions 13, a depth from the main surface 12 to the encapsulated regions 13 (distance from the main surface to top of the encapsulated region 13), represented by T, also has desired value. When the depth T is extremely small, top layers of cubic silicon carbide covered on the encapsulated regions 13 become extremely thin. Consequently, the encapsulated regions 13 are possibly exposed on the main surface 12 due to the damage of the top layer caused by their poor mechanical strength. Furthermore, when an activating region of semiconductor device is formed on the extremely thin top layer on the encapsulated regions 13, a uniform current flow through the substrate may be disturbed and it can cause local overheat or breakdown. Meanwhile, when the depth T is extremely large, the thermal strain of the layer between the encapsulated regions 13 and the main surface 12 can't be absorbed effectively. Consequently, reduction of the stacking faults density on the main surface 12. is not achieved. Therefore, depth T is desirable to be 100 nm or more and 100 μm or less, preferably 1 μm or more and 50 μm or less, and further preferably 10 μm or more and 30 μm or less in depth.

Considering the above description, the height H is desirable to be five times or more larger than the width S and the plane area of the encapsulated region 13 parallel to the main surface 12 is desirable to be 1/10 or less of the entire area of the main surface 12. Since the side wall, being a part of the encapsulated region, takes a major role for reducing stacking faults density, whole shape of the encapsulated regions has a lot of flexibility in the design as long as satisfying the aforementioned condition for the side wall and each dimension indicated in FIG. 1. For example, as for the encapsulated regions having a cross-sectional structure shown in FIG. 1, both of a line-space structure and a mesa structure are applicable, furthermore, each encapsulated region may also be connected inside the substrate without isolation.

As a method for fabricating the above mentioned silicon carbide substrate 1, the following method is available for example.

Undulation slopes parallel in [−110] direction are formed on Si(001) substrate as shown in the aforementioned patent document 2 and non-patent document 2. A maximum angle of this slope is desirable to be 2 degrees or more and 90 degrees or less. This is because, when the maximum angle is less than 2 degrees, an area of the polar face exposed at the edge of atomic steps becomes negligibly small compared with the area of non-polar (001) surface. Consequently, the defect reducing mechanism for anti-phase boundaries described in the silicon carbide epitaxial growth on the misoriented-Si(001) substrate does not work well. Meanwhile, when the maximum angle exceeds 90 degrees, the step-flow epitaxial growth is inhibited on the reverse tapered slopes.

These slopes of the adjacent undulations are continuously connected like a sinusoidal wave. Namely, the inclination angles of bottom and top of the undulations are 0 degree, and the inclination angle of the slope between bottom and top of the undulation is continuously varied from 0 degree to the maximum angle.

The cubic silicon carbide is grown on the aforementioned substrate. Although CVD, MBE, and LPE, etc., are available for cubic silicon carbide growth, the flow rate of Si-source and C-source are desirable to be individually adjustable in any case. Furthermore, supply ratios of the Si-source and C-source are preferably adjustable by precisely adjusting gas flow rates. When the growth rates are differentiated between Si-polar face and C-polar face by suitably adjusting the supply ratios of the Si-source and C-source, a specific crystal face is oriented in a specific orientation. In the case of Si-polar face, it is oriented to (111) plane or (−1-11) plane, and the C-polar face oriented to (−111) plane or (1-11) plane. Thus, by controlling the orientation of the polar face, the anti-phase boundary can be eliminated. The stacking faults, on the other hand, are remained on the substrate. All of them are distributed in {111} planes, corresponding to the closest-packed plane, and intersect with the main surface (001) surface at an angle of 54.7 degrees.

For example, according to a first embodiment described later, a lattice-shape patterned mask or a line-shape patterned mask with a width of 2 μm or more and 20 μm or less, and an interval of 2 μm or more and 30 μm or less, was formed on the aforementioned main surface using a photolithography technique. A material and a thickness of the mask are suitably selected in consideration of a stopping power against ion implantation, so that implanted ions are not passed through the mask pattern as described later.

After formation of the ion implantation mask, ions of any one of hydrogen, helium, neon, argon, krypton, and xenon, are implanted. Acceleration energy for implantation is suitably calculated so that a penetration depth of the ions is set to 1 μm or more and 20 μm or less. LSS theory described in the textbook entitled “Range concepts and heavy ion ranges” by J. Lindhard, M. Scharff, H. Schiotte, (Mat. Fys. Medd. Dan. Vid. Seisk. 33 (1963)1), is referred for this calculation. Since higher implantation energy is required for heavy ions, the light ion species, such as hydrogen and helium, are desirable. The implantation dose of the ions is determined so as to exceed a solubility limit in the cubic silicon carbide, and is preferably determined to obtain a density of 10²¹/cm³. For example, the implantation doze of the ion is determined to be 10¹⁷/cm² when the penetration depth of the ion is 10 μm.

After ion implantation process, cubic silicon carbide is grown on the main surface with similar condition of the aforementioned one. The growth thickness of the cubic silicon carbide is determined so as to ensure the desirable value of depth T, which is the distance from the main surface to top of the encapsulated region shown in FIG. 1. In other words, the growth thickness is given by the subtraction from the desirable depth T to a minimum penetration depth in the ion implantation corresponding to the top position of the encapsulated region. For example, when the desirable depth T is 10 μm and the minimum penetration depth in the ion implantation is 1 μm, the grown thickness will be 9 μm.

During this growth process, the encapsulated regions are formed by the education of the ion species implanted over the solubility limit in the cubic silicon carbide. Such encapsulated regions have the shape based on the aforementioned mask pattern, the height H determined by the penetration depth in the ion implantation and the side walls approximately parallel to {110} plane.

Hereafter, the four kinds of the embodiments will be described.

First Embodiment

The silicon carbide substrateaccording to a first embodiment of the present invention will be described hereafter.

First, in order to form the undulations in parallel to the [−110] direction, as shown in FIG. 9, on Si(001) surface, the polishing scratches were introduced on the surface of 4-inch Si(001) substrate by rubbing with the abrasive grains in one direction. Diamond slurry with a grain size of about 9 μm was used as the abrasive grains for introducing the polishing scratches. By rubbing the surface of the Si(001) substrate in a [−110] direction with a commercially available polishing cloth (EngisM414) soaked with this diamond slurry, innumerable polishing scratches which are approximately parallel with each other, were formed. A pressure for rubbing the surface of the substrate in a prescribed direction was set to 0.2 kg/cm², and the polishing cloth was reciprocally moved about 300 times in one direction to introduce the polishing scratches.

Next, in order to remove the residual abrasive grains on the processed surface, the following substrate cleaning was performed. After ultrasonic cleaning with pure water, the processed substrate was dipped in a mixed solution of a hydrogen peroxide solution and a sulfuric acid at a ratio of 1:1, and then a hydrofluoric acid solution. Then, a thermal oxide layer with a thickness of about 0.5 μm was formed on the processed substrate by sacrificial thermal oxidation, and thereafter the thermal oxide layer was removed by dilute hydrofluoric acid. Through the above described processes, the undulations, which are continuous wavy shape parallel to [−110] direction shown in FIG. 9, with a depth of a groove being 30 to 50 nm, a width of being 1 to 2 μm, and a gradient of being 3 to 5 degrees were obtained.

Next, in order to grow the thick cubic silicon carbide layer on the above described undulant-Si(001) substrate, the undulant-Si(001) substrate was heated up from room temperature to 1350 degree C. in a CVD apparatus. During heating up process, a mixed gas of C₂H₂ and H₂ was continuously supplied to form an ultrathin initial silicon carbide layer. The flow rates of C₂H₂ and H₂ and the growth pressure are shown in table 1.

TABLE 1 Supply amount of C₂H₂ 30 cc/min Supply amount of H₂ 100 cc/min Pressure 20 Pa

After the temperature of the substrate surface reached at 1350 degree C., supply of the mixed gas of C₂H₂ and H₂ was maintained for 15 minutes. Subsequently, SiH₂Cl₂ and C₂H₂ and H₂ were supplied at 1350 degree C. to hetero-epitaxially grow the thick silicon carbide layer. Note that growth conditions for growing the thick silicon carbide layer are shown in table 2. The growth pressure is adjusted by a pressure control valve installed in the middle of the exhaust line.

TABLE 2 Supply amount of SiH₂Cl₂ 50 cc/min Supply amount of C₂H₂ 10 cc/min Pressure 40 Pa Temperature 1,350° C.

The silicon carbide growth was performed for 8 hours under the growth conditions shown in Table 2 to grow 450-μm-thick cubic silicon carbide on the undulant-Si(001) substrate. Subsequently, wet etching of the undulant-Si(001) substrate with a mixed acid of hydrofluoric acid and nitric acid was performed to obtain free-standing 450-μm-thick single crystal cubic silicon carbide substrate.

Herein, in order to evaluate a defect density of the cubic silicon carbide substrate fabricated through the above described processes, the substrate was dipped into molten KOH at 500 degree C. for 5 minutes to expose the etch-pits on the surface. And then the etch-pits were observed by the optical microscopy. As a result, the stacking faults density of 2×10⁵/cm² and no anti-phase boundaries were observed on the entire main surface of the cubic silicon carbide substrate.

Next, in order to fabricate the metal mask for selective-area ion implantation, 500-nm-thick Ni layer was deposited on entire main surface using a vacuum evaporation deposition. Then, the positive photoresist layer of 2 μm in thickness was coated on the surface of the deposited Ni layer, and a square array pattern was formed by exposure to ultraviolet ray (g-line of mercury) using a photomask. Wherein, each side of an individual square pattern was aligned to be parallel to <110> orientation of the cubic silicon carbide substrate. A width of each side of the individual square pattern (corresponding to the interval W between the adjoining encapsulated regions 13 in FIG. 1) is 5 μm, and its interval (corresponding to the width S of the encapsulated region 13 in FIG. 1) is 2 μm, respectively.

Next, the dry etching of the Ni layer with a patterned photoresist mask was performed by F-plasma of 100 W. After that, the photoresist mask was completely removed by oxygen plasma. Finally, the lattice-shaped Ni mask with 5 μm square apertures aligned with keeping an interval of 2 μm was obtained. Next, proton ions were implanted vertically to the main surface. Wherein, the acceleration energy of protons is varied in a range of 10 keV to 400 keV, and their doses were determined by multiplying a target concentration 10²¹/cm³ by the penetration depth of the protons.

By aforementioned ion implantation, the proton irradiation regions (encapsulated regions) with a concentration of 10²¹/cm³ extending by 5 to 20 μm from the main surface were obtained. Wherein, height H of the encapsulated region was 15 μm, and the side walls of them were approximately parallel to {110} planes.

After removing the Ni mask, 5-μm-thick cubic silicon carbide layer was homo-epitaxially grown on the proton implanted substrate for 5 minutes under the growth conditions shown in Table 2. During this growth process, hydrogen was precipitated in the encapsulated regions at a depth of 10 to 25 μm from the surface.

Herein, in order to evaluate a defect density of the cubic silicon carbide substrate fabricated through the above described processes, the substrate was dipped into molten KOH at 500 degree C. for 5 minutes to expose the etch-pits on the surface. And then the etch-pits were observed by the optical microscopy. As a result, the stacking faults density of 2×10²/cm² was observed. In this embodiment, the stacking faults density could be reduced by 3 orders of magnitude by introducing the encapsulated regions. Furthermore, it was clearly observed that the propagation of the stacking faults induced by lattice strains is inhibited at the sidewalk of encapsulated regions.

Note that in this first embodiment, the undulations were formed on Si (001) substrate by rubbing with diamond slurry in one direction. However, the present invention is not limited thereto. For example, the combination of a lithography process and etching process could provide similar effects if the undulations have the same cross-sectional shape and arrangements as the first embodiment.

Furthermore, in this first embodiment, SiH₂Cl₂ and C₂H₂ were used as source gases for cubic silicon carbide growth. However, the present invention is not limited thereto. For example, SiH₄, SiCl₄, and SiHCl₃, etc. can be used as a source gas of silicon, and CH₄, C₂H₄, C₂H₆, and C₃H₈, etc. can be used as the source gas of carbon.

Furthermore, in this first embodiment, the cubic silicon carbide (001) face is used as the main surface of the silicon carbide substrate. However, the present invention is not limited thereto. For example, when the cubic silicon carbide (111) face is used as the main surface, {111}face, {110}face, or {211} face are applicable to the side wails of the encapsulated regions. Meanwhile, when a hexagonal silicon carbide {0001} face is used as the main surface, {11-20} face or {−1100}face are applicable to the side walls of the encapsulated regions. In this case, the closest-packed plane to which the stacking faults are propagated is corresponded to (0001) face, hence the stacking faults intersect with the main surface at an angle in the range of 30-60 degrees. Therefore, by executing the aforementioned each processes of this embodiment, similar effects as this embodiment can be obtained.

Furthermore, in this first embodiment, protons are used as the implantation ions. However, the present invention is not limited thereto. For example, implantation of the other ion species, such as He, Ne, Ar, Kr, Xe, and N, or a combination of them provides the similar effect as this embodiment if their penetration depth can satisfy a target depth (corresponding to height H of the encapsulated region 13 in FIG. 1).

Second Embodiment

The silicon carbide substrate according to a second embodiment of the present invention will be described hereafter.

First, similarly to the first embodiment of the present invention, the undulations were formed on the entire surface of 4-inch Si(001) substrate by rubbing with the abrasive grains in [−110] direction. Subsequently, the residual abrasive grains on the processed surface were cleaned off by the same cleaning process described in the first embodiment. Then, 0.5-μm-thick thermal oxide layer was formed on the undulant Si (001) substrate by sacrificial thermal oxidation and thereafter the thermal oxide layer was removed by a dilute hydrofluoric acid. Through the above described processes, the undulations, which are continuous wavy shape parallel to [−110] direction shown in FIG. 9, with a depth of a groove being 30-50 nm, a width of being 1-2 μm, and a gradient of being 3-5 degrees were obtained.

Next, in order to grow the thick cubic silicon carbide layer on the undulant Si(001) substrate, an ultrathin initial silicon carbide layer was grown under the growth condition in Table 1 described in the first embodiment.

Subsequently, 113-um-thick cubic silicon carbide layer, indicated by part 31 in FIG. 3, was grown for 2 hours under the growth conditions in Table 2.

Herein, in order to evaluate a defect density of the cubic silicon carbide substrate fabricated through the above described processes, the substrate was dipped into molten KOH at 500 degree C. for 5 minutes to expose the etch-pits on the surface. And then the etch-pits were observed by the optical microscopy. As a result, the stacking faults density of 8×10⁵/cm² and no anti-phase boundaries were observed on entire main surface.

Next, in order to fabricate the thermal SiO₂ mask for selective-silicon carbide growth, 100-nm-thick thermal SiO₂ layer was formed on entire main surface by dry oxidation at 1100 degree C. for 30 minutes. Then, the positive photoresist layer of 2 μm in thickness was coated on the surface of the thermal SiO₂ layer, and a square array pattern was formed by exposure to ultraviolet ray (g-line of mercury) using a photomask. Wherein, each side of an individual square pattern was aligned to be parallel to <110> orientation of the cubic silicon carbide substrate. A width of each side of the individual square pattern (corresponding to the width S of the encapsulated region 13 in FIG. 1) is 2 μm, and its interval (corresponding to the interval W between the adjoining encapsulated regions 13 in FIG. 1) is 5 μm, respectively.

Next, the dry etching of the thermal oxide layer with a patterned photoresist mask was performed by F-plasma of 100 W. After that, the photoresist mask was completely removed by oxygen plasma. Finally, the lattice-shaped thermal SiO₂ mask, shown in FIG. 2, with a plurality of square apertures 22 aligned with keeping constant interval 21 were obtained.

Subsequently, 10-μm-thick cubic silicon carbide layer was homo-epitaxially grown on the above described patterned substrate for 10 minutes under the growth conditions shown in Table 2. FIG. 3 shows a cross-sectional view of the cubic silicon carbide substrate after this growth process. As shown in FIG. 3, the silicon carbide homo-epitaxial layer 33 was selectively grown on a silicon carbide layer 31 through the apertures of the lattice-shaped SiO₂ mask 32.

Next, the substrate through the above described processes was dipped into a mixed acid of hydrofluoric acid and nitric acid to remove both of the thermal SiO₂ mask on surface and Si(001) layer on backside of the substrate. Consequently, as shown in FIG. 4, a plurality of isolated regions of single crystal silicon carbide 33 with a height of 10 μm, width of 2 μm, and interval of 5 μm were obtained on the 113-μm-thick silicon carbide layer 31.

Next, additional silicon carbide homo-epitaxial layer was grown on the isolated regions 33 in FIG. 4 to form the encapsulated regions. FIG. 5 shows the cross-sectional image of the cubic silicon carbide substrate after this additional growth. By the additional growth for 60 minutes under the condition shown in table 3, 10-μm-thick silicon carbide layer 41 was homo-epitaxially grown on the isolated regions 33 and bridged among them. Consequently, the encapsulated regions 42 with a width of 2 μm, an interval of 5 μm, and a height of 10 μm were obtained at 10 μm below the main surface.

TABLE 3 Supply amount of SiH₂Cl₂ 5 cc/min Supply amount of C₂H₂ 1 cc/min Supply amount of hydrogen 10 cc/min Pressure 4 Pa Temperature 1,450° C.

Herein, in order to evaluate a defect density of the cubic silicon carbide substrate fabricated through the above described processes, the substrate was dipped into molten KOH at 500 degree C. for 5 minutes to expose the etch-pits on the surface. And then the etch-pits were observed by the optical microscopy. As a result, the stacking faults density of 2×10²/cm² was observed on entire main surface. In the second embodiment, the stacking faults density could be reduced by about 3 orders of magnitude by introducing the encapsulated regions. Furthermore, it was clearly observed that the propagation of the stacking faults induced by lattice strains is inhibited at the sidewalls of encapsulated regions, and also observed that the encapsulated regions are formed while disappearing the stacking faults.

In this embodiment, the cubic silicon carbide (001) face is used as the main surface of the silicon carbide substrate. However, the present invention is not limited thereto. For example, the hexagonal silicon carbide can also be used with {11-20} plane and {03-38} plane as the main surfaces. In this case, the closest-packed plane to which the stacking faults are propagated is corresponded to (0001) face, hence the stacking faults intersect the main surface at an angle in the range of 30-60 degrees. Therefore, by executing the aforementioned each processes of this embodiment, similar effects as this embodiment can be obtained.

With respect to an effect of reducing the stacking faults density provided by present invention, some experimental results were presented hereafter. In the second embodiment, the encapsulated regions were formed at 10 μm below the main surface by the additional homo-epitaxial growth for 60 minutes under the condition shown in Table 3. Wherein, the location of the encapsulated regions depends on the thickness of the additional growth layer 41 and its location was closely related with the effect of reducing the stacking fault density on the main surface. Table 4 shows the relationship between the location of the encapsulated regions (depth of the encapsulated region) and the stacking faults density remaining on the main surface. It was found that an effect of reducing the stacking faults density becomes stronger with decreasing the depth of encapsulated region, especially 100 μm or below.

TABLE 4 Depth of encapsulated region Stacking faults density (μm) (/cm) 50 200 64 250 83 250 91 273 104 417 137 877 165 2,508 191 14,393 200 13,505

In addition to the above described defect density measurement, reverse characteristics measurement of p-n diodes fabricated on the silicon carbide substrate listed in Table 4 was performed. First, 3C—SiC homo-epitaxial layer was grown on the substrates listed in Table. 4 under the condition shown in Table 5. Through this homo-epitaxial growth process, 10-μm-thick n-type cubic silicon carbide layer with doping concentration of 5×10¹⁵/cm³ was obtained without intentional nitrogen doping.

TABLE 5 Supply amount of SiH₂Cl₂ 3 cc/min Supply amount of C₂H₂ 1 cc/min Supply amount of hydrogen 100 cc/min Pressure 4 Pa Temperature 1,550° C.

Then, Al ions were implanted to an entire surface of the homo-epitaxial layer to form p-n junction. An implantation depth is 1 μm, and an acceleration energy is adjusted in a range of 30-700 keV to obtain the constant doping profile of 1×10¹⁸/cm³ in a depth direction. After implantation of Al ions, activation annealing was applied to the surface at 1600 degree C. for 10 minutes in Ar atmosphere. Next, an array of Ni circular masks with a diameter of 100 μm was fabricated on the surface by a photolithography technique, and then rf-RIE was applied thereto for 5 minutes at 200 W with supplying a gas of CF₄(100 sec)+O₂(20 sccm). Finally, a plurality of mesa-type p-n diodes with a depth of 0.2 μm was obtained on the surface layer. Table 6 shows the leakage current density at reverse voltage of 600V for mesa-type p-n diodes fabricated on the substrates listed in Table 4. Reduction of a leakage current density was clearly demonstrated at a depth of the encapsulated region of 100 μm or below, particularly 50 μm.

TABLE 6 Depth of the encapsulated region Leak current density (μm) (A/cm²) 50 <2 × 10⁻⁸   64 4 × 10⁻⁷ 83 4 × 10⁻⁷ 91 1 × 10⁻⁶ 104 5 × 10⁻⁴ 137 2 × 10⁻³ 165 >2 × 10⁻³   191 >2 × 10⁻³   200 >2 × 10⁻³  

As described in the second embodiment, when a p-n diode was fabricated on the silicon carbide layer homo-epitaxially grown on the silicon carbide substrate including encapsulated regions with a depth of 100 μm or below, remarkable reduction of leakage current caused by the stacking faults was provided. This leakage current reduction effect was provided to not only a p-n diode but the other semiconductor device having similar internal electric field, such as a MOSFET type semiconductor device and so on.

Note that the cubic silicon carbide is used as the substrate in this embodiment, however, similar effects as this embodiment can be provided to the hexagonal silicon carbide substrate.

(Regarding the Reduction of the Stacking Faults)

A mechanism of reducing the stacking faults density on the surface of the substrate according to the second embodiment will be described. The mechanism of reducing the stacking faults in this embodiment was consisted of the following two manufacturing processes.

(1) Formation of the isolated regions (2) Reduction of the stacking faults density by homo-epitaxial growth

The details with respect to (1) and (2) are described hereafter.

(1) Formation of the Isolated Regions

FIG. 12 shows the cross-sectional image of isolated regions 210 formed on the (001) surface of cubic silicon carbide substrate 200. Wherein, isolated regions 210 are the elevated regions bounded by sidewalls of {110} planes. It is significantly preferable for the isolated regions 210 to have a side wall of {110} plane in the case of using the cubic silicon carbide (001) substrate. If the above condition is satisfied, there is no other condition with respect to the structure of the isolated regions 210. For example, a line-space structure or simple mesa-structure is applicable. Such isolated regions 210 can be fabricated through selective-growth or selective-etching process on mask-patterned silicon carbide substrate 200. Hereafter, it will be mainly explained in the case of the isolated regions 210 fabricated through selective-etching process on the cubic silicon carbide (001) substrate.

(2) Reduction of the Stacking Faults Density by Homo-Epitaxial Growth

FIG. 13 shows schematic diagram of reduction of the stacking faults density by homo-epitaxial growth. In principle, the stacking faults in the cubic silicon carbide (001) substrate 200 propagate at an angle of 54.7 degrees to the surface during the homo-epitaxial growth. With using this property, the stacking faults density can be significantly reduced by the following two mechanisms, named as mechanism M1 and mechanism M2.

<Mechanism M1>

First, the mechanism M1 will be described. As shown in FIG. 13, when the silicon carbide is homo-epitaxially-grown on the SiC substrate 200, stacking fault SF1, which is initially exposed on the surface without the isolated regions 210, is propagated into the homo-epitaxial layer. However, when the homo-epitaxial layer is grown up to the surface indicated by the dashed line 201, the stacking fault SF1 is inhibited its propagation into the isolated region 211 by the side walls. Such a reducing method of the stacking faults density is called as a mechanism M1. Note that when SiC is selectively grown on the mask-patterned substrate, as shown in the second embodiment, propagation of SF1 is inhibited by the mask on the surface.

<Mechanism M2>

Next, the mechanism M2 will be described. As shown in FIG. 13, the silicon carbide is homo-epitaxially grown on the SiC substrate 200, the stacking fault SF2, which is initially exposed on the surface within the isolated regions 210, is propagated into the homo-epitaxial layer.

When the homo-epitaxial layer is grown up to the surface indicated by the dashed line 201, the position of the stacking fault SF2 becomes closer to an edge of the isolated domain 211 than before. This is because the stacking fault SF2 moves toward the edge during the growth.

Finally, when the homo-epitaxial layer is grown up to the surface indicated by the solid line 202, the stacking fault SF2 reaches the side wall of the isolated domain 212 (i.e., SF2 reaches the encapsulated region) and being terminated there. Such a reducing method of the stacking faults density is called as the mechanism M2.

To achieve stacking fault termination described in Mechanism M2, the propagation rate of the stacking fault SF2 toward the edge of the isolated region should be faster than the growth rate of sidewalls in the <110> direction. This condition is expressed by the following formula (2), wherein r_(g[001]) indicates a growth rate in [001] direction and r_(g[110]) indicates a growth rate in <110> direction, respectively.

r _(g[001])/tan 54.7°−r _(g[110])>0  (2)

The ratio of a growth rate to satisfy the aforementioned formula can be controlled by adjusting a growth temperature, a supply ratio of a source gas, and a growth pressure.

Owing to the reduction of the stacking faults density by such mechanism M1 and mechanism M2, the stacking fault initially existed in the substrate 200 is significantly reduced, consequently a surface with extremely low stacking faults density can be obtained.

Third Embodiment

The silicon carbide substrate according to a third embodiment of the present invention will be described hereafter.

First, similarly to the first embodiment of the present invention, the undulations were formed on the entire surface of 4-inch Si(001) substrate by rubbing with the abrasive grains in [−110] direction. Subsequently, the residual abrasive grains on the processed surface were cleaned off by the same cleaning process described in the first embodiment. Then, 0.5-μm-thick thermal oxide layer was formed on the undulant Si (001) substrate by sacrificial thermal oxidation and thereafter the thermal oxide layer was removed by a dilute hydrofluoric acid. Through the above described processes, the undulations, which are continuous wavy shape parallel to [−110] direction shown in FIG. 9, with a depth of a groove being 30-50 nm, a width of being 1-2 μm, and a gradient of being 3-5 degrees were obtained,

Next, in order to grow the thick cubic silicon carbide layer on the undulant Si(001) substrate, an ultrathin initial silicon carbide layer was grown under the growth condition in Table 1 described in the first embodiment.

Subsequently, 113-um-thick cubic silicon carbide layer, indicated by part 31 in FIG. 3, was grown for 2 hours under the growth conditions in Table 2.

Herein, in order to evaluate a defect density of the cubic silicon carbide substrate fabricated through the above described processes, the substrate was dipped into molten KOH at 500 degree C. for 5 minutes to expose the etch-pits on the surface. And then the etch-pits were observed by the optical microscopy. As a result, the stacking faults density of 8×10⁵/cm² and no anti-phase boundaries were observed on entire main surface,

Next, in order to fabricate the thermal SiO₂ mask for selective-silicon carbide growth, 100-nm-thick thermal SiO₂ layer was formed on entire main surface by dry oxidation at 1100 degree C. for 30 minutes. Then, the positive photoresist layer of 2 μm in thickness was coated on the surface of the thermal SiO₂ layer, and a square array pattern was formed by exposure to ultraviolet ray (g-line of mercury) using a photomask. Wherein, each side of an individual square pattern was aligned to be parallel to <110> orientation of the cubic silicon carbide substrate. A width of each side of the individual square pattern (corresponding to the width S of the encapsulated region 13 in FIG. 1) is 2 μm, and its interval (corresponding to the interval W between the adjoining encapsulated regions 13 in FIG. 1) is 5 μm, respectively.

Next, the dry etching of the thermal oxide layer with a patterned photoresist mask was performed by F-plasma of 100 W. After that, the photoresist mask was completely removed by oxygen plasma. Finally, the lattice-shaped thermal SiO₂ mask, shown in FIG. 2, with a plurality of square apertures 22 aligned with keeping constant interval 21 were obtained.

Subsequently, 10-μm-thick cubic silicon carbide layer was homo-epitaxially grown on the above described patterned substrate for 10 minutes under the growth conditions shown in Table 2. Similarly to the second embodiment, the silicon carbide homo-epitaxial layer was selectively grown on a silicon carbide layer through the apertures of the lattice-shaped S102 mask.

Next, the substrate through the above described processes was dipped into a mixed acid of hydrofluoric acid and nitric acid to remove both of the thermal SiO₂ mask on surface and Si(001) layer on backside of the substrate. Consequently, as shown in FIG. 4, a plurality of isolated regions of single crystal silicon carbide with a height of 10 μm, width of 2 μm, and interval of 5 μm were obtained on the 113-μm-thick silicon carbide layer.

Next, polycrystalline silicon layer was grown on the entire surface of the above described silicon carbide substrate. FIG. 6 shows the cross-sectional image of the cubic silicon carbide substrate after this polycrystalline silicon growth. By the additional growth for 240 minutes under the condition shown in Table 7, 20-μm-thick polycrystalline silicon layer 53 was grown on both of surfaces of the isolated regions 52 and the valley between them.

Next, the polycrystalline silicon layer 53 was removed by polishing process to expose the single crystal silicon carbide on the surface of the isolated regions 52. FIG. 7 shows the cross-sectional image of the cubic silicon carbide substrate after this polishing process. By the surface polishing of 20-μm-thick polycrystalline silicon layer using diamond abrasive grains of 0.5 μm and 0.1 μm, the isolated regions 52 exposed single crystal silicon carbide surface surrounded with the polycrystalline silicon layer 53 were obtained.

Subsequently, silicon carbide homo-epitaxial layer was grown on the isolated regions 52 under the condition in Table. 3. During this homo-epitaxial growth, silicon carbide was preferably grown on the isolated regions 52 because on the polycrystalline silicon layer 53, thermal etching was dominant under this condition. FIG. 8 shows the cross-sectional image of the cubic silicon carbide substrate after this homo-epitaxial growth. By the homo-epitaxial growth for 10 minutes, 10-μm-thick silicon carbide layer 54 was homo-epitaxially grown on the isolated regions 52 and covered over the polycrystalline layer 53. Consequently, the encapsulated regions 53 made of the polycrystalline silicon with a width of 2 μm, an interval of 5 μm, and a height of 10 μm were obtained at 10 μm below the main surface.

TABLE 7 Supply amount of SiH₂Cl₂ 50 cc/min Supply amount of hydrogen 100 cc/min Pressure 35 Pa Temperature 1,050° C.

Herein, in order to evaluate a defect density of the cubic silicon carbide substrate fabricated through the above described processes, the substrate was dipped into molten KOH at 500 degree C. for 5 minutes to expose the etch-pits on the surface. And then the etch-pits were observed by the optical microscopy. As a result, the stacking faults density of 2×10²/cm² was observed on entire main surface. In the third embodiment, the stacking faults density could be reduced by about 3 orders of magnitude by introducing the encapsulated regions. Furthermore, it was clearly observed that the propagation of the stacking faults induced by lattice strains is inhibited at the sidewalls of encapsulated regions, and also observed that the encapsulated regions are formed while disappearing the stacking faults.

Note that in this embodiment, the encapsulated region consists of polycrystalline silicon. However, the present invention is not limited thereto. For example, the other materials, such as single crystal silicon, graphite, diamond-like carbon or silicon nitride provides the similar effect as this embodiment.

In this embodiment, the cubic silicon carbide (001) face is used as the main surface of the silicon carbide substrate. However, the present invention is not limited thereto. For example, the hexagonal silicon carbide can also be used with {11-20} plane and {03-38} plane as the main surfaces. In this case, the closest-packed plane to which the stacking faults are propagated is corresponded to (0001) face, hence the stacking faults intersect the main surface at an angle in the range of 30-60 degrees. Therefore, by executing the aforementioned each processes of this embodiment, similar effects as this embodiment can be obtained.

Fourth Embodiment

The silicon carbide substrate according to a fourth embodiment of the present invention will be described hereafter.

First, similarly to the first embodiment of the present invention, the undulations were formed on the entire surface of 4-inch Si(001) substrate by rubbing with the abrasive grains in [−110] direction. Subsequently, the residual abrasive grains on the processed surface were cleaned off through the following substrate cleaning. After ultrasonic cleaning with pure water, the processed substrate was dipped into a mixed solution of a hydrogen peroxide solution and a sulfuric acid at a ratio of 1:1, and then a hydrofluoric acid solution

Then, a thermal oxide layer with a thickness of about 0.5 μm was formed on the processed substrate by sacrificial thermal oxidation, and thereafter the thermal oxide layer was removed by dilute hydrofluoric acid. Through the above described processes, the undulations, which are continuous wavy shape parallel to [−110] direction shown in FIG. 9, with a depth of a groove being 30 to 50 nm, a width of being 1 to 2 μm, and a gradient of being 3 to 5 degrees were obtained.

Next, in order to grow the thick cubic silicon carbide layer on the undulant Si(001) substrate, an ultrathin initial silicon carbide layer was grown under the growth condition in Table 1 described in the first embodiment.

Subsequently, 113-um-thick cubic silicon carbide layer was grown for 2 hours under the growth conditions in Table 2.

Herein, in order to evaluate a defect density of the cubic silicon carbide substrate fabricated through the above described processes, the substrate was dipped into molten KOH at 500 degree C. for 5 minutes to expose the etch-pits on the surface. And then the etch-pits were observed by the optical microscopy. As a result, the stacking faults density of 8×10⁵/cm² and no anti-phase boundaries were observed on entire main surface.

Next, 500-nm-thick alumina layer was deposited on entire main surface of the silicon carbide substrate by RF-sputtering at room temperature. Polycrystalline alumina was used as a target and argon gas was used as a sputtering gas. During deposition for 15 minutes, applied RF power was 150 W and argon pressure was kept at 4×10⁻³ Torr.

Then, the positive photoresist layer of 2 μm in thickness was coated on the surface of the alumina layer, and a square array pattern was formed by exposure to ultraviolet ray (g-line of mercury) using a photomask. Wherein, each side of an individual square pattern was aligned to be parallel to <110> orientation of the cubic silicon carbide substrate. A width of each side of the individual square pattern (corresponding to the width S of the encapsulated region 13 in FIG. 1) is 2 μm, and its interval (corresponding to the interval W between the adjoining encapsulated regions 13 in FIG. 1) is 5 μm, respectively.

Next, the dry etching of the alumina layer with a patterned photoresist mask was performed by F-plasma of 100 W. After that, the photoresist mask was completely removed by oxygen plasma. Subsequently, the anodization was applied to the silicon carbide surface through the apertures of the alumina mask. Through the anodization under the condition in Table. 8, a plurality of porous silicon carbide regions having a width of 2 μm, an interval of 5 μm, and a depth of 10 μm were obtained. Wherein, the obtained porous silicon carbide had average porosity of 30%, and its depth was controlled by adjusting an applied voltage.

TABLE 8 Current density 0.1 A/cm² Solution HF:C₂H₅OH 1:1 Time  10 min Anode: silicon carbide Anode: W

After surface polishing using diamond abrasive grains of 0.1 μm to remove the alumina mask and obtain a smooth surface of the silicon carbide substrate, 10-μm-thick cubic silicon carbide layer was homo-epitaxially grown under the growth conditions shown in the aforementioned Table 2. Consequently, the encapsulated region made of a porous silicon carbide layer was formed at a depth of 10 to 20 μm from the main surface.

Herein, in order to evaluate a defect density of the cubic silicon carbide substrate fabricated through the above described processes, the substrate was dipped into molten KOH at 500 degree C. for 5 minutes to expose the etch-pits on the surface. And then the etch-pits were observed by the optical microscopy. As a result, the stacking faults density of 2.5×10²/cm² was observed on entire main surface. In the fourth embodiment, the stacking faults density could be reduced by about 3 orders of magnitude by introducing the encapsulated regions. Furthermore, it was clearly observed that the propagation of the stacking faults induced by lattice strains is inhibited at the sidewalls of encapsulated regions.

As described above in detail, according to the present invention, there is provided the silicon carbide substrate that can be preferably used as the substrate for the semiconductor device, by introducing the encapsulated regions in a suitable depth from the main surface, with their desired width, height, and interval, thereby blocking the stacking faults propagation in parallel to the closest-packed plane.

Note that the present invention is not limited to the aforementioned each embodiment, and may be variously modified unless departing from the scope of the present invention.

DESCRIPTION OF SIGNS AND NUMERALS

-   1 Silicon carbide substrate -   11 Cubic silicon carbide -   12 Main surface -   13 Encapsulated region -   14 Stacking fault 

1. A silicon carbide substrate having at least one or more main surfaces, comprising: a plurality of encapsulated regions inside, wherein the plurality of encapsulated regions are distributed in a direction approximately parallel to one of the main surfaces, with each encapsulated region positioned at a distance of 100 nm or more and 100 μm or less from the main surfaces to inside a substrate, and each encapsulated region having a width of 100 nm or more and 100 μm or less in a direction parallel to the main surfaces.
 2. The silicon carbide substrate according to claim 1, wherein each encapsulated region is formed including at least one of silicon, carbon, nitrogen, hydrogen, helium, neon, argon, krypton, and xenon.
 3. The silicon carbide substrate according to claim 1, wherein the encapsulated region is hollow.
 4. The silicon carbide substrate according to claim 1, wherein silicon carbide that forms the silicon carbide substrate is a plate-shaped single crystal.
 5. The silicon carbide substrate according to claim 1, wherein silicon carbide that forms the silicon carbide substrate is a cubic silicon carbide, with the main surface formed as (001) plane, and side walls of the encapsulated regions formed in parallel to {110} plane.
 6. The silicon carbide substrate according to the silicon carbide substrate of claim 1, wherein silicon carbide that forms the silicon carbide substrate is a cubic silicon carbide, with the main surface formed as (111) plane, and side walls of the encapsulated regions formed in parallel to {111} plane.
 7. The silicon carbide substrate according to claim 1, wherein silicon carbide that forms the silicon carbide substrate is a cubic silicon carbide, with the main surface formed as (111) plane, and side walls of the encapsulated regions formed in parallel to {110} plane or {211} plane.
 8. The silicon carbide substrate according to claim 1, wherein silicon carbide that forms the silicon carbide substrate is a hexagonal silicon carbide, with the main surface formed as {0001} plane, and side walls of the encapsulated regions formed in parallel to {11-20} plane or {−1100} plane.
 9. The silicon carbide substrate according to claim 1, wherein a width of the encapsulated region in a direction vertical to the main surfaces is five times or more of its width in a direction parallel to at least one of the main surfaces, and a cross-sectional area of the encapsulated region viewed from a direction parallel to the main surface is 1/10 or less of the area of the main surfaces.
 10. The semiconductor device using the silicon carbide substrate according to claim 1, wherein a silicon carbide layer having the same structure as a structure of the silicon carbide that forms the silicon carbide substrate, is formed on the main surface, and an internal electric field is formed on the silicon carbide layer. 